1. Field
The present invention relates to technology for data storage.
2. Description of the Related Art
Recent developments in semiconductor processing technologies and memory cell technologies have continued to increase the density achieved in integrated circuit memory arrays. For example, certain memory arrays may be fabricated having word lines approaching the minimum feature size (F) and minimum feature spacing for the particular word line interconnect layer, and also having bit lines approaching the minimum feature width and minimum feature spacing for the particular bit line interconnect layer. Moreover, three-dimensional memory arrays having more than one plane or level of memory cells have been fabricated implementing so-called 4F2 memory cells on each memory plane. Exemplary three-dimensional memory arrays are described in U.S. Pat. No. 6,034,882 to Johnson, entitled “Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication,” and in U.S. Pat. No. 5,835,396 to Zhang, entitled “Three-Dimensional Read-Only Memory Array.”
A three-dimensional memory array is most efficient when the number of memory cells on each bit line and word line is large. This number of cells is frequently called the fan-out (N) of the bit line or the word line. A large fan-out reduces the number of vertical connections between the array lines on each memory layer and the circuitry below. These vertical connections cannot lie beneath the individual memory cells on each layer, and thus may add significantly to the chip area. But a large fan-out frequently has certain electrical disadvantages depending on the memory cell technology being used. For example, the capacitance of array lines and the resistance of array lines may increase, and leakage per cell may cause power dissipation to increase. If the resistance on the bit line path is too high, a voltage drop can be experienced. Capacitance on the bit line path will affect sensing speed.